The present invention relates generally to a mask for electron beam exposure used in an exposure process in which an electron beam (EB) is irradiated onto a semiconductor wafer via the mask for electron beam exposure to pattern a resist film on the semiconductor wafer, and to a method of manufacturing a semiconductor device using such mask. More particularly, the present invention relates to a mask for electron beam exposure used in an exposure process which is performed by using an EB projection lithography system, and to a method of manufacturing a semiconductor device using such mask.
Conventionally, in a manufacturing process of a semiconductor device, an exposure process for exposing a resist film on a semiconductor wafer, here an electron beam resist film, with an electron beam was performed by using a cell projection EB system to pattern the resist film. In this system, an electron beam is irradiated onto an area of, for example, 125 micrometers(xcexcm)xc3x97125 micrometers of a mask for electron beam exposure. The mask for electron beam exposure has mask patterns comprising trenches or openings for passing an electron beam therethrough. An image of the mask patterns is reduced, for example, to {fraction (1/25)} and projected onto the semiconductor wafer by the electron beam passing through the mask for electron beam exposure. Therefore, by one shot of the exposure, an area of 5 micrometersxc3x975 micrometers on the semiconductor wafer, that is, an area of 5 micrometersxc3x975 micrometers of a resist film formed on the semiconductor wafer, is exposed by an electron beam having patterns corresponding to the mask patterns.
In order to fabricate one semiconductor device or one semiconductor chip, it is necessary to expose a resist film on a semiconductor wafer with patterns corresponding to one whole semiconductor chip, that is, patterns for a chip or chip patterns, and to pattern the resist film by the exposed chip patterns. In the cell projection EB system, a mask for electron beam exposure has a mask pattern area corresponding to a pattern area which is a part of an area of the patterns for one chip and which is repeated to obtain the patterns for one chip. Exposure steps by using such mask for electron beam exposure are repeated, while, for example, shifting the location of a semiconductor wafer with respect to the mask. Thereby, the resist film on the semiconductor wafer is exposed by the patterns for a chip, and is then developed to obtain a patterned resist film.
However, in the above-mentioned cell projection EB system, the area on the semiconductor wafer exposed at a time is not sufficiently large. Therefore, the number of electron beam shots required to expose a resist film on a semiconductor wafer by predetermined patterns for a chip becomes relatively large. As result thereof, the time required for an exposure process becomes long, and it is impossible to raise throughput of semiconductor manufacturing sufficiently high.
In order to realize a remarkable improvement in the throughput of semiconductor device manufacturing, there began to be proposed an EB projection lithography system, approximately from the year 1990. In this system, an electron beam having a large cross sectional area is used, and it becomes possible to irradiate the electron beam onto a relatively large area, for example, an area of 1 mmxc3x971 mm, on a mask for electron beam exposure, at a time. The mask for electron beam exposure has mask patterns comprising trenches or openings for passing an electron beam therethrough. Mask pattern image is reduced to, for example, xc2xc and projected onto a semiconductor wafer by the electron beam passing through the mask for electron beam exposure. Therefore, by one shot of exposure, it is possible to expose a large area on a semiconductor wafer, here an area of 250 micrometersxc3x97250 micrometers, by an electron beam having patterns corresponding to the mask patterns.
The inventor of the present invention studied and considered on a mask for electron beam exposure used in such EB projection lithography. As a result thereof, it was found that the mask for electron beam exposure can be fabricated as follows. A resist film on a semiconductor wafer must be exposed and patterned such that circuit patterns of a whole area of each chip, that is, patterns for a chip, are repeatedly exposed and formed. Patterns for one chip are divided into a plurality of small pattern areas or subfields, and patterns corresponding to each of the subfields are formed on one mask for electron beam exposure.
FIG. 6A is a plan view schematically showing a manner of dividing patterns for one chip into a plurality of subfields to fabricate a mask for electron beam exposure. FIG. 6B is a plan view showing a schematic structure of a mask for electron beam exposure considered by the inventor.
Patterns for one chip 115 are simply divided into a plurality of subfields per a maximum exposure area E2. The maximum exposure area is an area on a semiconductor wafer which is substantially exposed when it is assumed that the whole of an electron beam irradiated onto a mask for electron beam exposure passes thorough the mask for electron beam exposure and is exposed onto a semiconductor wafer by an exposure of one shot. In the above-mentioned example, a square area of 250 micrometersxc3x97250 micrometers on the semiconductor wafer corresponds to the maximum exposure area E2. In the example of FIG. 6A, a chip pattern area 115 is divided into 9 (nine) subfields S1 through S9, by division lines 116 provided every 250 micrometers both in a vertical direction and in a horizontal direction. Then, as shown in FIG. 6B, mask patterns which correspond to patterns obtained by enlarging the patterns of the subfields S1 through S9 four times respectively are formed in mask pattern areas M1-M9 between grillage areas 112 of a mask for electron beam exposure 105. In this case, the mask for electron beam exposure 105 is a 4xc3x97mask.
An electron beam is irradiated on each of the mask pattern areas M1 through M9 of the mask for electron beam exposure 105 shown in FIG. 6B, and predetermined portions of a resist film on the semiconductor wafer are sequentially exposed by the electron beam passed through the mask for electron beam exposure 105. In this case, the mask 105 and the semiconductor wafer are both intermittently shifted-relative to the electron beam. Thereby, the resist film formed on the semiconductor wafer can be exposed by the chip pattern 115 shown in FIG. 6A.
However, it is not always true that dimensions in a vertical direction and in a horizontal direction of the chip pattern 115 are respectively multiples of dimensions in a vertical direction and in a horizontal direction of the above-mentioned maximum exposure area, here both 250 micrometers. Therefore, the size and shape of all the subfields are not always constant. That is, the size of some of the subfields may become much smaller than that of the other subfields. Also, the shape of some of the subfields may become different from that of the other subfields. For example, in the: example of FIG. 6A, the size of each of the subfields S3, S6, S7, S8 and S9 located along the right side end and the upper side end of the chip pattern 115 becomes much smaller than the size of each of the other subfields S1, S2, S4 and S5, that is, 250 micrometersxc3x97250 micrometers. The dimensions of the mask pattern areas M1-M9 in a vertical direction and in a horizontal direction are four times the dimensions of the subfields F1-F9 in a vertical direction and in a horizontal direction, respectively. Therefore, as shown in FIG. 6B, among the mask pattern areas M1 through M9 of the mask for electron beam exposure 105, the size of each of the mask pattern areas M3, M6, M7, M8 and M9 formed along the right side end and upper side end becomes much smaller than that of each of the other mask pattern areas M1, M2, M4 and M5, that is, 1 mmxc3x971 mm.
The mask for electron beam exposure is fabricated by a process including an etching process for forming trenches or openings corresponding to the mask patterns on a wafer for fabricating the mask. In the mask for electron beam exposure 105 shown in FIG. 6B, in a process of etching a wafer for fabricating the mask, an etching rate of the trenches or openings for the mask pattern areas M3, M6, M7, M8 and M9 and an etching rate of the trenches or openings for the mask pattern areas M1, M2, M4 and MS differ much from each other due to the microloading effect. Therefore, the size of the trench or opening varies depending on the mask patterns, and there is a possibility that precision of sizes of the mask patterns formed on the mask for electron beam exposure is deteriorated. Thus, there is a possibility that the resist film having predetermined chip patterns is not formed with precision.
Also, in case the mask for electron beam exposure 105 shown in FIG. 6B is used, an electric current value of an electron beam passing through each of the mask pattern areas M3, M6, M7, M8 and M9 and an electric current value of an electron beam passing through each of the mask pattern areas M1, M2, M4 and M5 differ from each other largely. Therefore, a degree of electron beam blur of an electron beam irradiated onto a semiconductor wafer, caused by the coulomb effect, differs largely depending on which mask pattern area the electron beam has passed. Thus, there is a possibility that precision of sizes of the resist film patterns formed on the semiconductor wafer is deteriorated. Also, depending on the variation of degree of electron beam blur, degree of focusing an electron beam irradiated onto the semiconductor wafer also varies. It is difficult to perform an exposure process of a semiconductor wafer while compensating largely the degree of focusing an electron beam for each mask pattern area. When the variation of the degree of focusing an electron beam is large, there is a possibility that the variation of degree of focusing an electron beam is out of compensation by an exposure apparatus, and that the resist film on a semiconductor wafer is not exposed with predetermined patterns with precision.
Each of the mask pattern areas M1, M2, M4 and MS has the same size as that of an electron beam irradiation area E1 on the mask onto which an electron beam is substantially irradiated by one shot of exposure, that is, an area of 1 mmxc3x971 mm in the above-mentioned example. However, a distribution of intensity of an electron beam irradiated onto the mask for electron beam exposure is not completely uniform within the electron beam irradiation area E1 on the mask. In general, an intensity of an electron beam becomes lower in a peripheral portion than in the central portion. Therefore, a distribution of intensity of an electron beam irradiated onto each of the mask pattern areas M1, M2, M4 and M5 is not uniform within each mask pattern area, and an electron beam intensity in a peripheral area becomes smaller than that in the central area within each mask pattern area. Similarly, a distribution of intensity of an electron beam irradiated onto each of the mask pattern areas M3, M6, M7, M8 and M9 is not uniform within each mask pattern area. Therefore, the intensity of the electron beam irradiated onto the semiconductor wafer via the mask for electron beam exposure varies depending on the location on the semiconductor wafer, and there is a possibility that precision of sizes of the resist film patterns formed on the semiconductor wafer is deteriorated.
In the EB projection lithography system, a low magnification mask, such as 4xc3x97mask mentioned above, is used as a mask for electron beam exposure, taking a structure of the electron beam exposure apparatus in the system into consideration. This is because, if a high magnification mask is used in the EB projection lithography system, the sizes of the mask and a mask stage for placing the mask must be relatively large, so that it becomes difficult to accurately perform location control of the mask stage. Therefore, when compared with the above-mentioned conventional cell projection EB system in which a mask for electron beam exposure having a magnification from 25xc3x97 to 60xc3x97 is used, it is necessary to use, in the EB projection lithography system in which a low magnification mask is used, a mask for electron beam exposure in which mask patterns are more accurately formed.
Therefore, it is an object of the present invention to provide a mask for electron beam exposure which is usable with precision in an EB projection lithography system and a method of manufacturing a semiconductor device using such mask.
It is another object of the present invention to provide a mask for electron beam exposure by which a resist film on a semiconductor wafer can be precisely exposed with an electron beam of predetermined patterns and a method of manufacturing a semiconductor device using such mask.
It is still another object of the present invention to provide a mask for electron beam exposure by which predetermined resist film patterns can be precisely formed on a semiconductor wafer and a method of manufacturing a semiconductor device using such mask.
It is still another object of the present invention to provide a mask for electron beam exposure in which mask patterns are precisely formed and a method of manufacturing a semiconductor device using such mask.
It is still another object of the present invention to provide a mask for electron beam exposure by which a resist film on a semiconductor wafer can be precisely exposed with an electron beam of predetermined patterns and by which throughput of an exposure process can be improved and to provide a method of manufacturing a semiconductor device using such mask.
It is still another object of the present invention to provide a mask for electron beam exposure by which predetermined resist film patterns can be formed on a semiconductor wafer with precision and with high throughput and to provide a method of manufacturing a semiconductor device using such mask.
According to an aspect of the present invention, there is provided a mask for electron beam exposure used in a process for exposing a wafer with predetermined patterns for a chip by an EB projection lithography system, the mask comprising: a grillage area; a plurality of thin film areas surrounded by the grillage area and having a thickness thinner than that of the grillage area; and a plurality of mask pattern areas each of which is formed within respective one of the thin film areas, each of the mask pattern areas has mask patterns corresponding to patterns of a subfield obtained by dividing the patterns for a chip into a plurality of areas having substantially the same shape and size.
In this case, it is preferable that each of the mask pattern areas is smaller than an area irradiated by an electron beam on the mask for electron beam exposure when the electron beam is irradiated onto the mask for electron beam exposure.
It is also preferable that when the electron beam is irradiated onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas, the each of the mask pattern area is included within the area irradiated by the electron beam.
It is further preferable that when the electron beam is irradiated onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas, a distribution of intensity of the electron beam within each of the mask pattern areas is substantially uniform.
It is advantageous that the center of each of the mask pattern areas substantially resides in the center of each of the thin film areas surrounded by the grillage area.
It is also advantageous that a non-patterned area exists around each of the mask pattern areas and within corresponding one of the thin film areas.
It is further advantageous that each of the mask pattern areas verges on the grillage area.
It is also preferable that a space between the mask pattern areas is determined such that an area irradiated onto a mask pattern area by the electron beam does not overlap with other mask pattern areas when the electron beam is irradiated onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device which uses an EB projection lithography system, the method comprising: exposing a wafer with predetermined patterns for a chip by using a mask for electron beam exposure which mask has: a grillage area; a plurality of thin film areas surrounded by the grillage area and having a thickness thinner than that of the grillage area; and a plurality of mask pattern areas each of which is formed within respective one of the thin film areas, each of the mask pattern areas has mask patterns corresponding to patterns of a subfield obtained by dividing the patterns for a chip into a plurality of areas having substantially the same shape and size; wherein the wafer is exposed with predetermined patterns for a chip by performing, for each of the mask pattern areas, a step of irradiating an electron beam onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas.
It is preferable that each of the mask pattern areas is smaller than an area irradiated by the electron beam on the mask for electron beam exposure.
It is also preferable that when the electron beam is irradiated onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas, each of the mask pattern area is included within the area irradiated by the electron beam.
It is further preferable that the center of each of the mask pattern areas substantially resides in the center of each of the thin film areas surrounded by the grillage area.
It is advantageous that a non-patterned area exists around each of the mask pattern areas and within corresponding one of the thin film areas.
It is also advantageous that each of the mask pattern areas verges on the grillage area.
It is further advantageous that a space between the mask pattern areas is determined such that an area irradiated onto a mask pattern area by the electron beam does not overlap with other mask pattern areas when the electron beam is irradiated onto the mask for electron beam exposure such that the center of an area irradiated by the electron beam coincides with the center of each of the mask pattern areas.